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Semiconductor
SD60C32/P, SD60C52/P
CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER
Description
The AUK 60C32/P 60C52/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C52 contains a 8Kx8 ROM, a 256x8 RAM, 32 I/O lines, three 16bit counter/timers, a six sourc two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator , causing all other chip function to be inoperative.
Features
* * * * * * *
* 8-bit CPU optimized for control applications.
Pin-to-pin compatible with intel's 80C52/80C32. 256 Bytes of on-chip data RAM. 60C52 low power CPU only. 32 programmable I/O lines. Three 16bit timer/counters. TTL and CMOS compatible logic levels 64K external program memory space and data memory
* MCS-51 fully compatible instruction set * ONCETM (ON-circuit emulation) mode * Power control modes -Idle mode -Power down mode * 6 interrupt source space.
Ordering Information
Type NO. SD60C32 SD60C52 Marking SD60C32 SD60C52 Package Code PLCC44 PLCC44 Type NO. SD60C32P SD60C52P Marking SD60C32 SD60C52 Package Code DIP40 DIP40
SEATING PLANE 0.695 (17.399) BASE PLANE (17.653) 0.685 0.180 (4.572) 0.656 (16.662) 0.165 (4.191) 0.650 (16.510) 0.120 (3.048) 0.090 (2.286)
MIN 0.020 (0.508)
1
20 0.5MIN 4.5 0.3 3/4 3/4 3.5 0.3
0.050 (1.270) 0.630 (16.002) 0.590 (14.906)
PLCC44
KSI-W015-000
50.73/40.2 3/4
1.22TYP 1.4 0.13/4 0.1 2.54 3/4 0.5
DIP40
1
0.25
0.695 (17.653) 0.685 (17.399) 0.656 (16.662) 0.650 (16.510) 0.048 o (1.219) 0.042(1.067) 45
40
21
3/4 13.4 0.2 15.24
unit : mm
5A 1M X
Outline Dimensions
SD60C32/P SD60C52/P
Absolute Maximum Ratings
Characteristic
Ambient temperature under bias Storage temperature Voltage on any pin to VSS Maximum IOL per I/O pin Power dissipation
Rating
0 ~ +70 - 65 ~ + 150 - 0.5 ~ VCC + 0.5 15 1.5
Unit
E E V I W
Block Diagram Vcc Vss
P0.0-P0.7 PORT 0 DRIVERS
P2.0-P2.7 PORT 2 DRIVERS PORT 2 LATCH ROM/ EPROM
RAM ADDR RAM REGISTER
PORT 0 LATCH
B REGISTER
ACC TMP2 ALU PSW TMP1
STACK POINTER PROGRAM ADDRESS REGISTER
PSEN TIMING ALE AND EA RST CONTROL PD OSCILLATOR XTAL1 XTAL2
INSTRUCTION REGISTER
BUFFER PCON TMOD SCON TCON T2CON TL0 TH1 TH0 TL1 TH2 RCAP2H TL2 PC RCAP2L IE IP SBUF INCREINTERRUPT SERIAL MENTER PORT AND TIMER BLOCKS PROGRAM COUNTER DPTR
PORT 1 LATCH PORT 1 DRIVERS P1.0-P1.7
PORT 3 LATCH PORT 3 DRIVERS P3.0-P3.7
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SD60C32/P SD60C52/P
Pin Configuration
6 P1.4 5 P1.3 4 P1.2 3 P1.1/T2EX 2 P1.0/T2 1 NC 4 4V CC 43 P0.0/AD0 42 P0.1/AD1 41 P0.2/AD2 40 P0.3/AD3 44PLCC 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VP P 34 NC 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 18 WR/P3.6 19 RD/P3.7 20 XTAL2 2 XTAL1 1 V 22 SS NC 23 2 A8/P2.0 4 2 A9/P2.1 5 26 A10/P2.2 27 A11/P2.3 28 A12/P2.4
T2/P1.0 1 T2EX/P1.12 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.010 11 TxD/P3.1 12 INT0/P3.2 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.616 RD/P3.717 XTAL2 18 XTAL1 19 SS 20 V
40DIP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
V CC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P1.5 7 P0.5/AD5 P1.6 8 P0.6/AD6 P1.7 9 RST 10 P0.7/AD7 11 RxD/P3.0 EA/VP P NC 12 ALE/PROG 13 TxD/3.1 14 PSEN INT0/P3.2 15 P2.7/A15 INT1/P3.3 T0/P3.416 P2.6/A14 T1/P3.517 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Pin Description
VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP 40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP 40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's and source and sink several LS TTL inputs. Port 0 outputs the code bytes during program verification on the 60C52 external pullups resistors are required during program verification. Port 1 : PIN 1~8 (DIP 40), PIN 2~9 (PLCC44) Port 1 output buffers can drive LSI TTL inputs. Port 1 is an 8bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups KSI-W015-000 3
SD60C32/P SD60C52/P
Pin Description (Continued)
In addition, Port 1 serves the functions of the following special features of the 60C52. Port Pin P1.0 P1.1 Alternate Function T2(External Count Input to Timer / Counter 2) T2EX(Timer / Counter 2 Capture/Reload Trigger and Direction Control)
Port 1 receives the low-order address bytes during ROM verification. Port 2 : PIN 21~28 (40DIP), PIN 24~31 (44PLCC)
Port 2 is an 8-bit bi-directional I/O port with internal pullups. The port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as input. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8 bit addresses (MOVX @ Ri), port 2 emits the contents of the P2 special function register Port 3 : PIN 10~17 (DIP 40), PIN 13~19 (PLCC44) Port 3 is an 8bit bi-directional I/O port with internal pullups. The port 3 output buffers can drive LS TTL input. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below :
Port PIN
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
PIN NO.
10 11 12 13 14 15 16 17
Alternate Function
RxD (Serial input port) TxD (Serial output port) INT0 (External interrupt 0) INT1 (External interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (External data memory write strobe) RD (External data memory read strobe)
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SD60C32/P SD60C52/P
RST: PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC . ALE: PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input PROG during EPROM programming. PSEN : PIN 29 (DIP 40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA: PIN 31 (DIP 40), PIN 35 (PLCC44) External access enable. EA must be strapped to VSS in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. If EA is strapped to VCC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1: PIN 19 (DIP 40), PIN 21 (PLCC44) Input to the Inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2: PIN 18 (DIP 40), PIN 20 (PLCC44) Output from the inverting oscillator amplifier 0 Crystal Oscillator NC: PIN1, 12, 23, 34 (PLCC44) Non connection pins. 30pF 30pF XTAL1 VSS XTAL2
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SD60C32/P SD60C52/P
Idle Mode
In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
The control bits for the reduced power modes are in the special function register PCON. Table. Status of the external pins during Idle and power down modes.
Mode
Idle Idle Power Down Power Down
Program Memory
Internal External Internal External
ALE
1 1 0 0
PSEN
1 1 0 0
PORT 0 PORT 1 PORT 2 PORT 3
Data Float Data Float Data Data Data Data Data Address Data Data Data Data Data Data
KSI-W015-000
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SD60C32/P SD60C52/P
Electrical Characteristics (DC)
(Ta = 0 E ~ 70E or -40E ~ 85 E, VCC = 5V 20%, VSS =0V)
SYMBOL
VIL VIL1 VIH VIH1 VOL VOL1
PARAMETER
Input low voltage, except EA Input low voltage to EA Input high voltage, except XTAL1,RST Input high voltage to XTAL1, RST Output low voltage to ports 1,2,3 Output low voltage to ports 0, ALE, PSEN Output high voltage to ports 1,2,3,ALE,PSEN
LIMITS TEST CONDITIONS MIN TYP. MAX
-0.5 0 0.2VCC +0.9 0.7 VCC IOL=1.6I IOL=3.2I IOH=-60E IOH=-30E IOH=-10E IOH=-200E IOH=-3.2I IOH=-7.0I VIN =0.45V VIN =2V 0 < VI N < VCC VCC-0.3 VCC-0.7 VCC-1.5 VCC-0.3 VCC-0.7 VCC-1.5 -10 - 265 0.02 15 5 5 40 100 10 -50 -650 3/410 30 7.5 75 225 0.2VCC0.1 0.2VCC0.3 VCC+0.5 VCC+0.5 0.45 0.45
UNIT
V V V V V V
VOH
V
VOH1
Output high voltage (port 0 in external bus mode) Logical 0 input current to ports 1,2,3 Logical 1 to 0 transition current to ports 1,2,3 Input leakage current to port 0, EA Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode Internal reset pull-down resistor Pin capacitance
V
IIL ITL ILI
E E E I I E kohm pF
ICC
RRST C 1O
KSI-W015-000
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SD60C32/P SD60C52/P
Electrical Characteristics (AC)
(Ta = 0 E ~ 70E or -40E ~ 85 E, VCC = 5V 20%, VSS =0V)
SYSBOL
1/t CLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ
FIGURE
PARAMETER
Oscillator frequency : Speed Versions 60C32/60C52
12MHz CLOCK MIN MAX
VARIABLE CLOCK MIN MAX
3.5 16
UNIT
MHz A A A
1 1 1 1 1 1 1 1 1 1 1
ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse with PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float
127 43 53 234 53 205 145 0 59 312 10
2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 tCLCL-30 3tCLCL-45 3 CLCL-105 0 tCLCL-25 5tCLCL-105 10
A A A A A A A A
Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL 4 4 4 4 High time Low time Rise time Fall time 20 20 20 20 20 20 20 20 A A A A 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR High RD low to address float RD or WR high to ALE high 43 200 203 33 33 433 0 123 tCLCL-40 0 107 517 585 300 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL-40 400 400 252 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 A A A A A A A A A A A A A A
KSI-W015-000
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SD60C32/P SD60C52/P
Electrical Characteristics (Continued)
(Ta = 0 E ~ 70E or -40E ~ 85 E, VCC = 5V 20%, VSS =0V)
SYMB FIGUR OL E
1/t CLCL t LHLL t AVLL t LLAX t LLIV t LLPL t PLPH t PLIV t PXIX t PXIZ t AVTV t PLAZ t RLRH t WLWH t RLDV t RHDX t RHDZ t LLDV t AVDV t LLWL t AVWL t ZVWX t WHQX t QVWH t RLAZ t WHLH 1 1 1 1 1 1 1 1 1 1 1
PARAMETER
Oscillator frequency : Speed Versions 60C52/60C32 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse with PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float
16MHz CLOCK MIN MAX
VARIABLE CLOCK UNI T MIN MAX
3.5 16 MHz A A A 4t CLCL-100 t CLCL-40 3t CLCL-45 A A A 3CLCL-105 0 t CLCL-25 5t CLCL-105 10 A A A A A
85 23 33 150 23 143 83 0 38 208 10
2t CLCL-40 t CLCL-40 t CLCL-30
Data Memory 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR High RD low to address float RD or WR high to ALE high 23 138 120 13 13 288 0 103 t CLCL-40 0 55 350 398 238 3t CLCL-50 4t CLCL-130 t CLCL-50 t CLCL-50 7t CLCL-150 0 t CLCL+40 275 275 148 0 2t CLCL-70 8t CLCL-150 9t CLCL-165 3t CLCL+50 6t CLCL-100 6t CLCL-100 5t CLCL-165 A A A A A A A A A A A A A A
External Clock t CHCX t CLCX t CLCH t CHCL 4 4 4 4 High time Low time Rise time Fall time 20 20 20 20 20 20 20 20 A A A A
KSI-W015-000
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SD60C32/P SD60C52/P
Timing Diagram tLHLL ALE t AVLL PSEN PORT0 PORT2 tPLPH tLLPL tLLIV tPLIV tLLAX t tPXIX t XIZ PLAZ P A0 - A7 tAVIV INSTR IN A0 - A7 A8 - A15
A0 - A15
Figure 1. External Program Memory Read Cycle
ALE tWHLH PSEN RD tAVLL PORT0 PORT2 t LAX t LDV L R tRHDZ tRLAX tRHDX A0 - A7 INSTR FROM RI OR DPL DATA IN A0 - A7 FROM PCL IN tAVWL tAVDV P2.0 - P2.7 OR A8 - A15 FROM A0 - A15 FROM PCH DPH tLLDV tLLWL tRLRH
Figure 2. External Data Memory Read Cycle
KSI-W015-000
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SD60C32/P SD60C52/P
Timing Diagram (Continued)
ALE tWHLH PSEN tLLWL WR PORT0 PORT2 tAVLL tLLAX tWLWH tQVWX tWHQX
A0 - RI DATA OUT FROMA7 OR DPL tAVWL
A0 - A7 FROM PCL INSTR IN
P2.0 - P2.7 OR A8 - A15 FROM DPH - A15 FROM PCH A0
Figure 3. External Data Memory Write Cycle
V- 0.5 0.7V CC CC -0.1 tCHCX 0.45V 0.2V SS tCHCLtCLCXtCLCH tCLCL Figure 4. External Clock Drive
V+ 0.1V LOAD+ V 0.1V OH TIMING +0.9 V LOAD REFERENCE 0.2V CC POINTS + V- 0.1V V 0.1V LOAD OL -0.1 0.2V CC 0.45V NOTE : For timing purposes, a port is no longer flo NOTE : AC Inputs during testing are driven logic 100mV change from load voltage occurs, a CC for a at V -0.5 to float when OH the /V '1' and 0.45V for a logic '0'. Timing measurements are a 100mV change fromOL lo level occurs. OH L 20mA /I A OI made at min for a logic '1'for a logic '0' IH V ILand V Figure 5. AC Testing Input/Output Figure 6. Float Waveform -0.5 V CC
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SD60C32/P SD60C52/P
Timing Diagram (Continued) 45 40 35 30 25 ICC 20 I 15 10 5 MAX IDLE MODE TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz FREQ AT XTAL1 Figure Icc vs. FREQ 7. Valid only within frequency specifications of the device under test V CC I CC V CC RST (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS P0 EA V CC RST V CC P0 EA V CC I CC V CC TYP ACTIVE MODE MAX ACTIVE MODE
(NC) XTAL2 CLOCK SIGNAL XTAL1 V SS
Figure 8. I CC Test Condition, Active Mode All other pins are disconnected
Figure 9. I CC Test Condition, Idle Mode All other pins are disconnected
KSI-W015-000
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SD60C32/P SD60C52/P
Timing Diagram (Continued)
CC V - 0.5 0.45V
C 0.7VC -S tCHCX 0.2V 0.1 S tCHCL tCLCX tCLCH tCLCL
Figure 10. Clock Signal Waveform cfor I in Active and Idle Modes c Tests t CLCH tCHCL= 5A =
V CC ICC RST V CC V CC P0 EA (NC) XTAL2 XTAL1 V SS
Figure 11. cI Test Condition, Power down Mode c All other pins are disconnected, = 2V to 5.5V cc V
KSI-W015-000
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